1. Field of the Invention
The present invention relates to the architecture of data processing systems which make use of microprocessors intercommunicating by means of a common system channel or BUS. More particularly, it relates to the priority mechanism which allows the common use of the BUS among the several microprocessors.
2. Description of Prior Art
Large Scale Integration (LSI) or microprocessor components are being used more and more in computer and data processing systems. Such components are widely utilized to perform the functions of central processing units or interface control units which are connected to the peripheral devices.
An example of such integrated components or microprocessors is the Z-80 ZILOG Trademark microprocessors family of the ZILOG Corporation. Such family includes, for example, a microprocessor identified as Z-80 CPU central processing units which performs the specific functions of a central control unit in a data processing system, and a miroprocessor identified as Z-80 PIO (Parallel Input/Output microprocessor) which performs interface control functions in connecting peripheral devices through parallel channels to the systems. Another microprocessor of the family identified as Z-80 SIO (Serial Input/Output microprocessor) performs an interface control function in connecting peripheral devices through a serial channel to the system. These interface microprocessors such as Z-80 PIO and Z-80 SIO will be referred to herein as "processors".
A simple system built up with such family components may include, for example, a central unit Z-80 CPU, an oscillator for the generation of timing signals, a power supply for the generation of a +5 V regulated voltage, a read only memory for containing the microprograms required for the operation of the system and a processor Z-80 PIO (or SIO) coupled to an input/output peripheral unit such as a keyboard/printer. More complex systems may include, in addition to the read only memory, one or more read/write working memories for storage of data and programs, and a plurality of processors such as Z-80 PIO (or SIO) each connected to the common system BUS.
This kind of architecture makes possible the assembling of flexible systems, based on modular elements which can be added or removed according to need, to obtain the most suitable configuration for the required functions.
For example a system can be materially built up as a chassis or rack where a number N of printed circuit boards can be housed. The rack is provided with a plurality N of connector sockets for such printed circuit boards. The corresponding contact elements of each connector socket are all connected together by means of "wire-wrap" technology or preferably by means of conductive leads formed on a printed circuit board. This board is usually called the "back panel". These parallel connection leads materially form the system BUS.
A printed circuit board can include the microprocessor Z-80 CPU, the oscillator and other possible circuits. A second board can include a control Read Only Storage (ROS) memory. One or several additional boards can include a read/write working memory, one or several interface processors each, or whatever else is required. In such a structure it is possible to reconfigure the system by adding or taking away boards within the capacity N of the rack to house such boards. Thus a single product design satisfies the needs of several users or the different needs of the same user.
Unfortunately a system reshaping and expansion which can be obtained by the simple adding or changing of printed circuit boards has some limitations at the present state of the art. These limitations are substantially imposed by the competing requests of several processors for access to a common BUS or CPU control unit. Each processor can send an interrupt request signal to the CPU central unit through a lead specifically assigned to each processor. The plurality of such leads for each processor is connected to the input of a network which detects interruptions and selects one of them on a priority basis. Such network acts as intermediary between the several "processors" and the central unit CPU, presenting to the central unit only one interruption at a time and selecting the highest priority processor.
The selection operation requires a group of leads, each one dedicated to a processor; that is, it connects the selection network to a processor. In order to have a system which can be reshaped, a prearranged recognition and selection network suitable for the maximum number of processors that the system architecture contains is required, and therefore a great waste of components is generally involved. The prior art selection means makes use of a high number of interconnection leads equal to twice the maximum number of processors that the system may contain.
In recent system architectures, these problems are avoided by providing a selection network which only utilizes one interruption lead for all interruption request signals. Also in order to execute a prioritary selection, each processor is furnished with an internal masking mechanism. This mechanism allows the inhibition or masking of the interruption request generated from each processor, if such processor detects the presence of a higher priority interruption request. The priority of each processor is determined by its position in an inhibition chain.
Each processor has an interruption enabling input (IEI) and an interruption enabling output (IEO). By coupling the output IEO of each processor with the input IEI of another processor, a chain is formed in which an orderly priority is awarded to the several processors.
The identification of the interrupting processor occurs through the sending on the BUS lead of an "interrupt vector" which supplies directly or indirectly the identity of the interrupting processor. It is possible to extend and reshape the system utilizing the invention without the need to prearrange a plurality of interruption handling leads and a suitable priority newtwork. Nevertheless the interruption masking mechanism requires the transfer of a signal in the chain of processors with a propagation time from processor to processor in the order of 200 nanoseconds and strictly limits the number of processors which can be effectively connected to the BUS.